Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow symmetrical source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or an ion implantation process. Without the sidewall spacers, the doping process vertically introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is vertically doped a second time to form the deeper source and drain regions. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacer.
As transistors disposed on integrated circuits (ICs) become smaller, and critical dimensions of MOSFETS are reduced, proper design and engineering of source/drain extensions becomes more critical to the operation of small-scale transistors. In conventional MOSFET structures, the source extension and the drain extension are formed in the same fabrication process step. For example, as stated above, the source extension and drain extension can be formed in the same ion implantation step or the same impurity thermal defusion step. Accordingly, the source extension and the drain extension generally have identical characteristics. For example, the source extension and the drain extension can have an identical dopant profile, dopant concentration, junction concentration, and junction depth.
Generally, a shallow source extension provides better immunity to short channel effects, such as, threshold voltage-roll off and drain induced barrier lowering. The parasitic series resistance of the source extension also plays an important role in transistor drive current. The larger the source extension resistance, the smaller the gate-to-source bias (Vgs), and hence the smaller the transistor drive current. Accordingly, the source extension should be as conductive as practicable. In contrast, the drain extension may not be as important as the source extension in terms of control of short channel effects and drive current. However, it does play an important role in transistor reliability.
Thus, there is a need for a transistor with optimized source and drain extensions. Further, there is a need for a method of manufacturing a transistor that has asymmetrical source and drain extensions. Further still, there is a need for transistors that have immunity to short channel effects and low drive current and yet have suitable reliability. Even further still, there is a need for a transistor having a deeper, more lightly doped drain extension than the source extension and a method of manufacturing such a transistor.